1. Field of the Invention
The invention relates to an electrostatic discharge protection circuit, and more particularly to an electrostatic discharge protection circuit for an output circuit.
2. Description of the Related Art
For general circuit design, a circuit set is required in a circuit for preventing the circuit from damage by static electricity from human bodies or the environment, which would reduce operating lifespan of the circuit.
The circuit set is usually referred to an electrostatic discharge (ESD) prevention circuit. In prior art, there are two types of ESD prevention circuit designs.
One circuit design disposes a Ballast resistor in the ESD prevention circuit, which prevents a parasitic NPN transistor from being non-uniformly turned on. Specifically, the disposition of the Ballast resistor decreases the non-uniform turned on condition of the parasitic NMOS.
The other circuit design disposes an ESD clamp circuit between power lines for conducting a portion or all of the currents. FIG. 1 is a conventional output circuit with an ESD clamp circuit. Referring to FIG. 1, an output circuit 1 comprises an ESD clamp circuit 11 coupled between a voltage source VCC and a ground terminal 12. The output circuit 1 further comprises a PMOS transistor 13, an NMOS transistor 14, a parasitic diode 15, and an output unit 16. A source of the PMOS transistor 13 is coupled to the voltage source VCC, and a drain thereof is coupled to the output unit 16. A source of the NMOS transistor 14 is coupled to the ground terminal 12, and a drain thereof is coupled to the output unit 16. The parasitic diode 15 is coupled to the voltage source VCC, and the output unit 16 is coupled to the parasitic diode 15. In a PS mode (ESD stress on the input or output pins with the VSS pin relatively grounded), the ESD clamp circuit 11 can conduct the electrostatic current to flow from the parasitic diode 15 sequentially to the voltage source VCC, the ESD clamp circuit 11, and the ground terminal 12, thereby decreasing damage from the electrostatic current.
For a large sized output circuit application, low on-state resistance (RDSON) is usually required, however, a Ballast resistor can increase RDSON. Assuming costs for a low RDSON requirement and a smaller layout size are considered usually, there is no Ballast resistor or a very small Ballast resistor in a large sized output circuit. Thus, a parasitic NPN transistor of an ESD prevention circuit of the example, will often be non-uniform turned on. When the non-uniform turned-on condition occurs in a large sized open drain NMOS (ODNMOS) transistor, the ESD problem of the output circuit becomes more serious. This is because an electrostatic discharge current has to pass through the NMOS transistor 14, rather than from the parasitic diode 15, due to not having a forward biased diode, and sequentially to the voltage source VCC, the ESD clamp circuit 11, and the ground terminal 12 of FIG. 1. FIG. 2 is an output circuit with large sized open drain NMOS (ODNMOS). Referring to FIG. 2, in an output circuit 2, a first parasitic capacitor 21 and a second parasitic capacitor 22 are used to provide voltage dividing, so that a first NMOS transistor 23 is turned on non-uniformly. In practice, however, the voltage source VCC is charged through the first parasitic capacitor 21 and a parasitic diode 25 when ESD occurs. When a capacitance between a voltage source VCC and a ground terminal is greater than the value of the first parasitic capacitor 21, the voltage source VCC is charged to an insufficiently high potential. Thus, making the potential of the gate of the first transistor 23 not high enough, and the impedance of the channel of the turned-on first NMOS transistor 23 too high, degrading the ESD protection. Additionally, when the second NMOS transistor 24 is in a turned-on state, the potential of the gate of the first transistor 23 is pulled to the ground terminal, and the ESD prevention is further degraded.
Meanwhile, following is another problem of the ESD prevention in a large sized output circuit application. When an ESD event test is preformed to pins, the ESD event test is passed in a PS-mode but failed in a positive I/O-to-I/O mode. This is because the potential of the gate of the first transistor 23 is pulled to a low logic level according to circuitry logic. FIG. 3 shows the correlation between an output circuit with large sized open drain NMOS and pins. Referring to FIG. 3, in an output circuit 3, potential of an input terminal 31 is lower than potential of a ground terminal 32. For an inverter S1, the lower potential serves as a low logic level. After an even-stage circuit, the (2n)th inverter S2n also outputs a low potential. Thus, lowering the potential of the gate of the first NMOS 23, and degrading the ESD prevention.